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coreboot/src/soc
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Barnali Sarkar b57772d2bf intel/skylake: Update UPD parameters as per FSP 1.8.0 
Some MemoryInit UPD parameters have been moved to
SiliconInit in FSP 1.8.0. This patch has the respective
changes in coreboot for this.

BRANCH=none
BUG=none
TEST=Build and booted in kunimitsu

CQ-DEPEND=CL:*237423, CL:*237424

Change-Id: Ic008d22f96fb5f14965e5b5db15e05fb39dd52d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 573c1d8325cd504213528030ecf99559402b5118
Original-Change-Id: I71b893aa7788519ed2ef15f3247945ffcbbbcf4d
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310191
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 20:40:05 +01:00
..
broadcom/cygnus Correct some common spelling mistakes 2016-01-07 22:57:02 +01:00
imgtec/pistachio imgtec/pistachio: disable default RPU gate register values 2015-12-31 17:36:06 +01:00
intel intel/skylake: Update UPD parameters as per FSP 1.8.0 2016-01-15 20:40:05 +01:00
marvell/bg4cd arm/arm64: Generalize bootblock C entry point 2015-11-11 05:08:07 +01:00
mediatek/mt8173 tree: drop last paragraph of GPL copyright header from new files 2016-01-13 20:35:40 +01:00
nvidia Correct some common spelling mistakes 2016-01-07 22:57:02 +01:00
qualcomm/ipq806x cbfs_spi: enable CBFS access in early romstage 2015-12-03 14:17:04 +01:00
rockchip/rk3288 google/veyron*: Pulse the i2c clock once if sda was low 2015-11-18 16:29:16 +01:00
samsung soc/samsung/exynos5250: Implement hard_reset() 2015-12-16 00:41:03 +01:00
ucb/riscv tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00