Angel Pons b5320b2dc1 soc/intel/baytrail: Rename "pmc.h" to "pm.h" ... This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I3d4c1285bdc4b061383b7bb6262f69671166b9c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>		2020-07-09 12:46:35 +00:00
..
acpi	acpigen: Add acpigen_notify	2020-07-07 20:31:22 +00:00
arch	arch/x86: Add memmove.c to x86 bootblock	2020-07-08 21:06:47 +00:00
commonlib	lib/coreboot_table: Add Intel FSP version to coreboot table	2020-07-04 11:20:08 +00:00
console
cpu	haswell: relocate romstage_common to northbridge	2020-07-08 22:16:58 +00:00
device	Kconfig: Escape variable to accommodate new Kconfig versions	2020-06-19 15:29:04 +00:00
drivers	dptf: Add support for IDSP	2020-07-07 17:23:47 +00:00
ec	ec/google: Add function ec_fill_dptf_helpers()	2020-07-07 20:31:30 +00:00
include	ACPI: Add and fill gnvs_ptr for smm_runtime	2020-07-08 07:32:51 +00:00
lib	lib: Temporarily remove timestamps from psp_verstage	2020-07-08 19:37:50 +00:00
mainboard	soc/intel/baytrail: Rename "pmc.h" to "pm.h"	2020-07-09 12:46:35 +00:00
northbridge	haswell: relocate romstage_common to northbridge	2020-07-08 22:16:58 +00:00
security	security/vboot: Allow files to go into only RW-A or RW-B region	2020-07-08 19:36:24 +00:00
soc	soc/intel/baytrail: Rename "pmc.h" to "pm.h"	2020-07-09 12:46:35 +00:00
southbridge	sb/intel/lynxpoint: Program PM registers directly	2020-07-08 22:26:15 +00:00
superio	superio/winbond/w83977tf: Add suspend related fields	2020-06-16 20:17:26 +00:00
vendorcode	vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc	2020-07-07 22:24:41 +00:00
Kconfig	arch/x86: Remove RELOCATABLE_RAMSTAGE	2020-07-06 06:17:47 +00:00