Wonkyu Kim b4d7116a74 soc/intel/tigerlake: Delete unused configuration ... Delete below configuration - Heci3Enabled: deprecated, see https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h#n442 - PchIshEnable: don't need as it's handled by devicetree dev on/off, see https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/romstage/fsp_params.c#n87 BUG🅱️151166877 BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: If96cc7db7118dd6c2ac02aab3bb0c96763ffc722 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2020-05-26 15:10:57 +00:00
..
amd	soc/amd/picasso: Give the mainboard the ability to modify the MADT table	2020-05-26 14:37:22 +00:00
cavium	src: Remove leading blank lines from SPDX header	2020-05-18 07:00:27 +00:00
intel	soc/intel/tigerlake: Delete unused configuration	2020-05-26 15:10:57 +00:00
mediatek	soc/mediatek/mt8183: Set CA and DQ vref range to correct value	2020-05-20 09:50:45 +00:00
nvidia	src: Remove leading blank lines from SPDX header	2020-05-18 07:00:27 +00:00
qualcomm	src: Remove unused 'include <string.h>'	2020-05-18 07:41:24 +00:00
rockchip	src: Remove leading blank lines from SPDX header	2020-05-18 07:00:27 +00:00
samsung	samsung/exynos5420: add resources during read_resources()	2020-05-14 21:27:34 +00:00
sifive	src: Remove leading blank lines from SPDX header	2020-05-18 07:00:27 +00:00
ucb	treewide: Remove "this file is part of" lines	2020-05-11 17:11:40 +00:00