Angel Pons b45a769939 soc/intel: Add Kaby Lake PCH-U base device ID ... Taken from Intel document 334658-003 (7th Generation Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel Processor Family I/O for U Quad Core Platforms, Datasheet - Volume 1 of 2). Change-Id: I1d48c8868e1e5d453d599ecec835938ce09935d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52702 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-04-28 14:14:35 +00:00
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alderlake	soc/intel/alderlake: Use device ID from pci_devs header file	2021-04-26 08:27:54 +00:00
apollolake	soc/intel: Move pmc_soc_set_afterg3_en() to pmutil.c	2021-04-21 09:17:40 +00:00
baytrail	soc/intel/baytrail/pmutil.c: Define __SIMPLE_DEVICE__	2021-04-19 10:45:15 +00:00
braswell	soc/intel/braswell/pmutil.c: Define __SIMPLE_DEVICE__	2021-04-19 10:45:06 +00:00
broadwell	haswell/broadwell: Replace remaining MCHBAR accessors	2021-04-26 18:39:58 +00:00
cannonlake	soc/intel/cannonlake: set MSR LT_LOCK_MEMORY at end of POST	2021-04-22 22:44:57 +00:00
common	soc/intel: Add Kaby Lake PCH-U base device ID	2021-04-28 14:14:35 +00:00
denverton_ns	soc/intel/dnv_ns: hook up new gpio device operations	2021-04-08 06:49:55 +00:00
elkhartlake	soc/intel/elkhartlake: Remove elog.c	2021-04-26 08:32:20 +00:00
icelake	soc/intel: Replace open-coded buffer length calculation	2021-04-21 14:21:44 +00:00
jasperlake	soc/intel/jasperlake: Remove TCSS setting from the DMAR table	2021-04-23 14:48:04 +00:00
quark	mainboards: Drop PWRS from GNVS	2021-02-11 16:35:32 +00:00
skylake	soc/intel: Add Kaby Lake PCH-U base device ID	2021-04-28 14:14:35 +00:00
tigerlake	soc/intel/tigerlake: Use device ID from pci_devs header file	2021-04-26 08:27:34 +00:00
xeon_sp	soc/intel/xeon_sp/cpx: Add UPI locks	2021-04-23 14:52:14 +00:00
Kconfig