Taniya Das 91dc1e74a5 sc7180: clock: Fix QUP DFSR configuration for perf levels ... Update the QUP DFSR cmd to clear the SW control and also update the perf registers when M is set. While at it also update the d_2 values. Tested: validated DFSR clock configuration and M/N/D values. Change-Id: I6bba1c6f99810963aaa607885ef400c523c0e905 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>		2020-02-07 23:12:00 +00:00
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common
ipq40xx	src/soc/qualcomm: Remove unused <stdlib.h>	2019-12-19 04:07:13 +00:00
ipq806x	src/soc/qualcomm: Remove unused <stdlib.h>	2019-12-19 04:07:13 +00:00
qcs405	soc/qualcomm/qcs405: Remove unused QCS405_BLSP_SPI	2020-01-02 14:31:31 +00:00
sc7180	sc7180: clock: Fix QUP DFSR configuration for perf levels	2020-02-07 23:12:00 +00:00
sdm845	soc/qualcomm/sdm845: Remove unused 'include <timestamp.h>'	2019-12-19 05:18:51 +00:00
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