Robert Zieba b3b27f7dea soc/amd/mendocino: Enable GPP clk req disabling for disabled devices ... Enable GPP clk req disabling for disabled PCIe devices. If a clk req line is enabled for a PCIe device that is not actually present and enabled then the L1SS could get confused and cause issues with suspending the SoC. BUG=b:250009974 TEST=Ran on skyrim proto device, verified that clk reqs are set appropriately Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68139 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>		2022-10-26 22:02:32 +00:00
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amd	soc/amd/mendocino: Enable GPP clk req disabling for disabled devices	2022-10-26 22:02:32 +00:00
cavium	soc/cavium,ti: Do resource transition	2022-06-29 11:55:01 +00:00
example/min86	src/mb: Add SPDX identifiers to files missing them	2022-08-11 17:52:19 +00:00
intel	coreboot_tables: Drop uart PCI addr	2022-10-26 14:12:06 +00:00
mediatek	coreboot_tables: Drop uart PCI addr	2022-10-26 14:12:06 +00:00
nvidia	coreboot_tables: Drop uart PCI addr	2022-10-26 14:12:06 +00:00
qualcomm	coreboot_tables: Drop uart PCI addr	2022-10-26 14:12:06 +00:00
rockchip	soc/rockchip/rk3288/clock.c: Remove trailing semicolon	2022-09-30 23:12:15 +00:00
samsung	coreboot_tables: Drop uart PCI addr	2022-10-26 14:12:06 +00:00
sifive/fu540	src/soc: Get rid of most src/soc/Kconfig files	2022-06-24 03:59:36 +00:00
ti	coreboot_tables: Drop uart PCI addr	2022-10-26 14:12:06 +00:00
ucb/riscv	src/soc: Get rid of most src/soc/Kconfig files	2022-06-24 03:59:36 +00:00