Arthur Heymans b38d6bbe1c soc/intel/xeon_sp/cpx: Align coreboot CAR symbols to FSP-T ... The CAR set up by FSP-T is at base 0xfe800000 and has a 0x200000 size. FSP-M seems to have a very large stack usage so it would overflow other car symbols located below the coreboot stack such as timestamps and the pre-ram console, which are now fixed. TEST: boot with ocp/deltalake. Change-Id: I886f9391ad79fcfa0724109393e3781a08d954b4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46895 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-11-04 08:27:31 +00:00
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alderlake	soc/intel: Select SOC_INTEL_COMMON_BLOCK_CAR as per alphabetical order	2020-11-03 04:07:02 +00:00
apollolake	soc/intel: Use of common reset code block	2020-11-02 10:43:53 +00:00
baytrail	src: Include <arch/io.h> when appropriate	2020-10-26 06:44:40 +00:00
braswell	src: Include <arch/io.h> when appropriate	2020-10-26 06:44:40 +00:00
broadwell	soc/intel/broadwell: Relocate PCH ACPI files	2020-11-03 19:12:35 +00:00
cannonlake	soc/intel: Use of common reset code block	2020-11-02 10:43:53 +00:00
common	soc/intel/common/block/systemagent/memmap.c: Align cached region	2020-11-03 17:04:03 +00:00
denverton_ns	soc/intel/denverton_ns: Add PCH_DEVFN_PMC for finding PMC device	2020-11-02 06:28:50 +00:00
elkhartlake	soc/intel: Select SOC_INTEL_COMMON_BLOCK_CAR as per alphabetical order	2020-11-03 04:07:02 +00:00
icelake	soc/intel: Select SOC_INTEL_COMMON_BLOCK_CAR as per alphabetical order	2020-11-03 04:07:02 +00:00
jasperlake	soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix	2020-11-03 23:58:45 +00:00
quark
skylake	soc/intel: Use of common reset code block	2020-11-02 10:43:53 +00:00
tigerlake	soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix	2020-11-03 23:58:45 +00:00
xeon_sp	soc/intel/xeon_sp/cpx: Align coreboot CAR symbols to FSP-T	2020-11-04 08:27:31 +00:00
Kconfig