coreboot

History

Dennis Wassenberg 498c32a6e8 siemens/sitemp_g1p1: Fix serial output for simo board The simo board with console output at UART port 1 (COM2) will not produce any output if CONFIG_UART_FOR_CONSOLE=1 is set correctly. Commit `f29200240e` (superio/ite/*: Factor out generic romstage component) will only and always activate UART port 0 unregarded to CONFIG_UART_FOR_CONSOLE value. Now the UART port which was selected by CONFIG_UART_FOR_CONSOLE will be enabled and used for console output Change-Id: Ibbd2b5115b1ed4763962ba32fc9c19431a906c78 Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com> Reviewed-on: http://review.coreboot.org/7060 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>	2014-10-24 10:38:26 +02:00
..
sitemp_g1p1	siemens/sitemp_g1p1: Fix serial output for simo board	2014-10-24 10:38:26 +02:00
Kconfig

Dennis Wassenberg 498c32a6e8 siemens/sitemp_g1p1: Fix serial output for simo board

The simo board with console output at UART port 1 (COM2) will not produce
any output if CONFIG_UART_FOR_CONSOLE=1 is set correctly.
Commit f29200240e
(superio/ite/*: Factor out generic romstage component)
will only and always activate UART port 0 unregarded to
CONFIG_UART_FOR_CONSOLE value.
Now the UART port which was selected by CONFIG_UART_FOR_CONSOLE
will be enabled and used for console output

Change-Id: Ibbd2b5115b1ed4763962ba32fc9c19431a906c78
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Reviewed-on: http://review.coreboot.org/7060
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

2014-10-24 10:38:26 +02:00

sitemp_g1p1 siemens/sitemp_g1p1: Fix serial output for simo board 2014-10-24 10:38:26 +02:00

Kconfig