Alicja Michalska 4d9549b95f soc/intel: Add definition of D0 stepping for TigerLake Halo ... Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>		2024-03-05 23:29:17 +00:00
..
amd	include/cpu/amd/msr: introduce and use PSTATE_MSR_COUNT	2023-07-18 21:51:33 +00:00
intel	soc/intel: Add definition of D0 stepping for TigerLake Halo	2024-03-05 23:29:17 +00:00
power	src/cpu/power9: move part of scom.h to scom.c	2023-04-18 13:05:56 +00:00
x86	cpu/x86/(sipi|smm): Pass on CR3 from ramstage	2024-02-28 12:12:59 +00:00
cpu.h	x86: Separate CPU and SoC physical address size	2023-12-22 12:26:59 +00:00