Patrick Georgi b20a600ba7 intel/fsp1_0: Declare microcode to be size 0 if it doesn't exist ... Change-Id: Id2063fb29226dcb55fe84f680b7b9cb10313ef2b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11753 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>		2015-09-30 06:56:47 +00:00
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acpi
arch	x86: prepare cache-as-ram to allow multiple stages	2015-09-30 06:53:55 +00:00
commonlib	commonlib: add endian related accessor functions	2015-09-22 21:21:56 +00:00
console
cpu	coreboot: move TS_END_ROMSTAGE to one spot	2015-09-24 16:12:44 +00:00
device	symbols: add '_' to pci_drivers and cpu_drivers symbols	2015-09-05 15:36:23 +00:00
drivers	intel/fsp1_0: Declare microcode to be size 0 if it doesn't exist	2015-09-30 06:56:47 +00:00
ec	chromeec: Fix ACPI compile warnings	2015-09-28 09:34:13 +00:00
include	chromeos: vboot and chromeos dependency removal for sw write protect state	2015-09-23 19:35:31 +00:00
lib	program.ld: terminate ALIGN statement	2015-09-28 09:36:50 +00:00
mainboard	glados: Provide nau8825 platform data via _DSD	2015-09-28 09:35:13 +00:00
northbridge	coreboot: move TS_END_ROMSTAGE to one spot	2015-09-24 16:12:44 +00:00
soc	skylake: select HAVE_INTEL_FIRMWARE	2015-09-29 13:56:05 +00:00
southbridge	intel: auto include intel/common/firmware	2015-09-29 13:55:52 +00:00
superio
vendorcode	chromeos: vboot-related functions move to common vboot code	2015-09-29 22:35:47 +00:00
Kconfig	Kconfig: Remove EXPERT mode	2015-08-30 07:50:47 +00:00