Xiang Wang b1e6654d86 riscv: use mret to invoke M-mode payload and disable interrupts ... Fixes a logic error that sets MPIE, but didn't use mret to return to the payload. This left MIE set to an undefined value. Now all modes are handled the same way: - Trap vector base address point to the payload - Disable Interrupt - Return to payload using mret TEST=Run an M-mode payload Change-Id: Iaab595f916949c57104ec00f8b06ea047fe76bba Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33462 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-06-23 12:14:54 +00:00
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arm	arch: Add missing #include <commonlib/helpers.h>	2019-06-21 16:04:06 +00:00
arm64	arch: Add missing #include <commonlib/helpers.h>	2019-06-21 16:04:06 +00:00
mips	arch/mips: Fix <arch/mmio.h> prototypes	2019-03-22 12:18:41 +00:00
ppc64	arch/ppc64: Add <arch/mmio.h> stubs	2019-03-21 15:58:34 +00:00
riscv	riscv: use mret to invoke M-mode payload and disable interrupts	2019-06-23 12:14:54 +00:00
x86	arch: Add missing #include <commonlib/helpers.h>	2019-06-21 16:04:06 +00:00