Eric Lai 086f0faf75 soc/intel/cannonlake: Move GPIO PM configuration to soc level ... Enable GPIO clock gating when enter s0ix/Sx and save the PM bits. Restore the PM bits when exit s0ix/Sx. BUG=b:144002424 TEST=Check GPIO PM bits when enter/exit s0ix are expected Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I120f8369b8d3cf7ac821332bdfa124f6ed0570e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>		2019-12-26 10:51:22 +00:00
..
amd	soc/amd/picasso: Configure APOB NV only with ACPI resume	2019-12-26 10:48:06 +00:00
cavium	soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h>	2019-12-19 05:38:43 +00:00
intel	soc/intel/cannonlake: Move GPIO PM configuration to soc level	2019-12-26 10:51:22 +00:00
mediatek	soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell	2019-12-20 17:57:03 +00:00
nvidia	src/soc/nvidia: Remove unused <stdlib.h>	2019-12-19 04:06:52 +00:00
qualcomm	src: Remove unused include <string.h>	2019-12-26 10:45:37 +00:00
rockchip	src: Replace min/max() with MIN/MAX()	2019-12-20 17:49:29 +00:00
samsung	src/soc/samsung: Remove unused <stdlib.h>	2019-12-19 05:39:09 +00:00
sifive	src: Replace min/max() with MIN/MAX()	2019-12-20 17:49:29 +00:00
ucb	mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.	2019-12-06 15:09:48 +00:00