coreboot/src
Angel Pons b053583a1c nb/intel/gm45: Use PCI bitwise ops
While we are at it, also reflow a few lines that fit in 96 characters.

Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: Icaca44280acdba099a5e13c5fd91d82c3e002bae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42189
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-04 12:22:04 +00:00
..
acpi src/acpi: Add missing <{stdbool,stdint}.h> 2020-07-29 09:37:10 +00:00
arch mb/emulation/qemu-armv7: Fix board 2020-08-03 05:11:17 +00:00
commonlib src: Remove unused 'include <stdint.h> 2020-07-14 16:11:10 +00:00
console console: Update for vboot before bootblock 2020-06-15 22:07:12 +00:00
cpu cpu/intel/haswell: add Crystal Well CPU IDs 2020-08-03 05:16:29 +00:00
device Change all assert(0) to BUG() 2020-08-03 05:15:15 +00:00
drivers drivers/ipmi/ocp: Add ipmi set processor information 2020-08-03 05:24:27 +00:00
ec ec/lenovo/h8: Align macro values in one column 2020-07-26 21:40:00 +00:00
include src/lib: Remove unused function parameters in imd.c 2020-08-04 07:13:59 +00:00
lib src/lib: Remove unused function parameters in imd.c 2020-08-04 07:13:59 +00:00
mainboard mb/**/{devicetree,overridetree}.cb: Indent with tabs 2020-08-04 12:21:14 +00:00
northbridge nb/intel/gm45: Use PCI bitwise ops 2020-08-04 12:22:04 +00:00
security security/intel/txt: Add Intel TXT support 2020-07-31 16:02:54 +00:00
soc soc/amd/picasso: set is_rv to 1 for RV family 2020-08-03 15:12:03 +00:00
southbridge Change all assert(0) to BUG() 2020-08-03 05:15:15 +00:00
superio superio/common: Avoid NULL pointer dereference 2020-07-24 21:21:09 +00:00
vendorcode vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments 2020-08-02 16:45:22 +00:00
Kconfig arch/x86: Remove RELOCATABLE_RAMSTAGE 2020-07-06 06:17:47 +00:00