Kyösti Mälkki 59e0334207 AGESA: Switch to MMCONF_SUPPORT_DEFAULT ... Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2016-12-01 05:49:09 +01:00
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abm	AGESA: Switch to MMCONF_SUPPORT_DEFAULT	2016-12-01 05:49:09 +01:00
dl145_g1	src/mainboard/getac - kontron: Add space around operators	2016-09-20 21:54:45 +02:00
dl145_g3	src/mainboard/getac - kontron: Add space around operators	2016-09-20 21:54:45 +02:00
dl165_g6_fam10	Kconfig: Update default hex values to start with 0x	2016-10-02 19:08:15 +02:00
e_vectra_p2706t	intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP	2016-06-21 00:39:47 +02:00
pavilion_m6_1035dx	AGESA: Switch to MMCONF_SUPPORT_DEFAULT	2016-12-01 05:49:09 +01:00
Kconfig
Kconfig.name