coreboot/src/arch
Duncan Laurie 3235d727de UPSTREAM: acpi: Generate object for coreboot table region
Generate an object to describe the coreboot table region in ACPI
with the HID "CORE0000" so it can be used by kernel drivers.

To keep track of the "CORE" HID usage add them to an enum and add
a function to generate the HID in AML:  Name (_HID, "CORExxxx")

BUG=chromium:589817
BRANCH=none
TEST=build and boot on chell, dump SSDT to verify contents:

Device (CTBL)
{
    Name (_HID, "CORE0000")  // _HID: Hardware ID
    Name (_UID, Zero)  // _UID: Unique ID
    Method (_STA, 0, NotSerialized)  // _STA: Status
    {
        Return (0x0F)
    }
    Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
    {
        Memory32Fixed (ReadOnly,
            0x7AB84000,         // Address Base
            0x00008000,         // Address Length
            )
    })
}

Change-Id: Ifa39e378eb1e7c00f03d8d213f52ff3cb9c17606
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16056
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/368714
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
2016-08-12 13:45:10 -07:00
..
arm UPSTREAM: src/arch: Capitalize CPU, RAM and ROM 2016-08-04 23:37:18 -07:00
arm64 UPSTREAM: arm64: Add stack dump to exception handler 2016-05-26 03:21:55 -07:00
mips build system: remove CBFSTOOL_PRE1_OPTS 2016-05-03 11:40:49 +02:00
power8 UPSTREAM: region: Add writeat and eraseat support 2016-06-27 17:13:18 -07:00
riscv UPSTREAM: src/arch/riscv/id.S: Don't hardcode the strings 2016-08-11 20:39:57 -07:00
x86 UPSTREAM: acpi: Generate object for coreboot table region 2016-08-12 13:45:10 -07:00