Felix Held af356d313d soc/amd/sabrina: use correct PCI IDs ... Replace the Renoir/Cezanne PCI IDs with the Sabrina ones that were added in commit 27b02c2eee (include/device/ pci_ids.h: add PCI IDs for AMD Family 17h Model A0h SoC). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I427df6f8e8c08fb47ae8513b6cf1085d4294e28f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>		2022-01-25 03:19:24 +00:00
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cezanne	soc/amd/{common,cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZE	2022-01-23 16:42:48 +00:00
common	soc/amd/common/block/include/psp_efs: update defines for sabrina	2022-01-25 03:18:58 +00:00
picasso	soc/amd/{common,cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZE	2022-01-23 16:42:48 +00:00
sabrina	soc/amd/sabrina: use correct PCI IDs	2022-01-25 03:19:24 +00:00
stoneyridge	soc/amd/*/chip.h: add missing gpio.h include	2022-01-13 18:08:14 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00