Karthikeyan Ramasubramanian af331a96cc vc/amd/fsp/sabrin/bl_uapp_header: Add SoC FW ID at the right offset ... SoC FW ID needs to be populated at offset 0x58 and 0x59 in the PSP header. BUG=b:217414563 TEST=Build Skyrim BIOS image and ensure that PSP verstage is getting loaded. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ibe7b26aea0567e5337ee3e6e9447aa3944c55f5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2022-07-20 14:10:56 +00:00
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amd	vc/amd/fsp/sabrin/bl_uapp_header: Add SoC FW ID at the right offset	2022-07-20 14:10:56 +00:00
cavium	rules.h: Use more consistent naming	2022-05-16 21:52:22 +00:00
eltan	vc/eltan/security/verified_boot/Makefile: add fmap_config.h dependency	2022-02-22 15:56:03 +00:00
google	treewide: Unify Google branding	2022-07-04 14:02:26 +00:00
intel	vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP v3257_00_40	2022-07-19 23:32:11 +00:00
mediatek	vc/mediatek/mt8195: Fix rank1 CKE setting for single-rank DRAM	2021-12-01 09:48:17 +00:00
siemens	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
Makefile.inc	soc/mediatek/mt8192: initialize DRAM using vendor reference code	2021-03-08 03:15:43 +00:00