This is a new port for the Intel DQ67SW desktop board. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM. A list of tested working and non-working features is in the documentation page. Change-Id: Ifc703f2d0ad45495e71d3f7799347430f5196791 Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> |
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| .. | ||
| _static | ||
| acpi | ||
| arch | ||
| community | ||
| contributing | ||
| drivers | ||
| getting_started | ||
| gfx | ||
| infrastructure | ||
| lib | ||
| mainboard | ||
| northbridge | ||
| releases | ||
| RFC | ||
| sbom | ||
| security | ||
| soc | ||
| superio | ||
| technotes | ||
| tutorial | ||
| util | ||
| vendorcode | ||
| .gitignore | ||
| .mdl_style.rb | ||
| acronyms.md | ||
| AMD-S3.txt | ||
| beginverbatim.tex | ||
| cbfs.txt | ||
| codeflow.svg | ||
| conf.py | ||
| COPYING | ||
| coreboot_logo.bmp | ||
| coreboot_logo.png | ||
| coreboot_logo.svg | ||
| corebootBuildingGuide.tex | ||
| distributions.md | ||
| documentation_license.md | ||
| endverbatim.tex | ||
| external_docs.md | ||
| gcov.txt | ||
| hypertransport.svg | ||
| index.md | ||
| Makefile | ||
| Makefile.sphinx | ||
| payloads.md | ||
| POSTCODES | ||
| util.md | ||