coreboot/src/soc
Benjamin Doron ac857ca3b1 soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration
coreboot already unconditionally enables CLKRUN_EN in SoC common code.

Tested on an out-of-tree Acer Aspire VN7-572G, PCCTL[CLKRUN_EN]
of LPC is still enabled.

Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48325
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17 20:05:49 +00:00
..
amd soc/amd/cezanne: add GPIO definitions 2020-12-17 14:48:50 +00:00
cavium cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
example x86: Add a minimal example SoC along with a board 2020-10-30 21:34:18 +00:00
intel soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration 2020-12-17 20:05:49 +00:00
mediatek soc/mediatek/mt8192: Do the dramc pinmux selection 2020-12-16 08:03:59 +00:00
nvidia drivers: Replace set_vbe_mode_info_valid 2020-12-17 06:21:56 +00:00
qualcomm cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
rockchip drivers: Replace set_vbe_mode_info_valid 2020-12-17 06:21:56 +00:00
samsung cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
sifive cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
ti cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
ucb soc/ucb/riscv: Add chip_operations stub 2020-05-28 09:30:35 +00:00