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Sridhar Siricilla abe0d810f0 soc/intel/alderlake: Log CSE RO write protection info for ADL 
The patch logs CSE RO's write protection information for Alder Lake
platform. As part of write protection information, coreboot logs status
on CSE RO write protection and range. Also, logs error message if EOM
is disabled, and write protection for CSE RO is not enabled.

TEST=Verify the write protection details on Gimble.

Excerpt from Gimble coreboot log:
	[DEBUG]  ME: WP for RO is enabled        : YES
	[DEBUG]  ME: RO write protection scope - Start=0x1000, End=0x15AFFF

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30 23:55:15 +00:00
..
acpi coreboot_tables.c: Expose the ACPI RSDP 2022-03-09 14:21:01 +00:00
arch prog_loader: Change legacy_romstage_select_and_load() to return cb_err 2022-03-09 17:20:48 +00:00
commonlib commonlib/timestamp_serialized: Add timestamp enum to name mapping 2022-03-30 21:21:53 +00:00
console src/console/Kconfig: Add option to disable loglevel prefix 2022-03-30 00:02:34 +00:00
cpu cpu/x86/smm: Add weak SoC init and exit methods 2022-03-10 17:06:51 +00:00
device device/pci_device.c: Return if the scan parameter is invalid 2022-03-30 00:03:08 +00:00
drivers drivers/tpm: Force enable long IRQ pulses for Ti50 versions under 0.15. 2022-03-30 13:40:30 +00:00
ec ec/starlabs/merlin: Add GLKR variant 2022-03-30 14:22:50 +00:00
include commonlib/bsd/helpers: Remove redundancy with libpayload defines 2022-03-30 21:21:47 +00:00
lib lib/device_tree.c: zero-initialize new DT nodes 2022-03-22 20:45:26 +00:00
mainboard mb/google/skyrim: Call espi_switch_to_spi1_pads 2022-03-30 22:42:01 +00:00
northbridge nb/intel/sandybridge/acpi: Support setting PCI bars above 4G 2022-03-28 15:28:19 +00:00
security {drivers/security}: Replace cb_err_t with enum cb_err 2022-03-09 08:40:43 +00:00
soc soc/intel/alderlake: Log CSE RO write protection info for ADL 2022-03-30 23:55:15 +00:00
southbridge sb/amd/hudson/spi.c: Use C over CPP conditional 2022-03-25 20:06:57 +00:00
superio Use the fallthrough statement in switch loops 2022-02-16 21:29:53 +00:00
vendorcode ChromeoS: Retain ACPI CNVS contents on S3 resume 2022-03-30 21:43:00 +00:00
Kconfig src/Kconfig: Update the path to 'c_start.S' for GDB_STUB config 2022-02-22 20:49:10 +00:00