abde3b56ce
Secure monitor runs at EL3 and is responsible for jumping to the payload at
specified EL and also to manage features like PSCI.
Adding basic implementation of secure monitor as a rmodule. Currently, it just
jumps to the the payload at current EL. Support for switching el and PSCI will
be added as separate patches.
CQ-DEPEND=CL:218300
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles succesfully and secure monitor loads and runs payload on ryu
Change-Id: If0f22299a9bad4e93311154e5546f5bae3f3395c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5e40a21115
Original-Change-Id: I86d5e93583afac141ff61475bd05c8c82d17d926
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214371
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9080
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
77 lines
2.4 KiB
C
77 lines
2.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2003 Eric Biederman
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef CONSOLE_CONSOLE_H_
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#define CONSOLE_CONSOLE_H_
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#include <stdint.h>
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#include <rules.h>
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#include <console/post_codes.h>
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#include <console/loglevel.h>
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#ifndef __ROMCC__
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void post_code(u8 value);
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#if CONFIG_CMOS_POST_EXTRA
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void post_log_extra(u32 value);
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struct device;
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void post_log_path(struct device *dev);
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void post_log_clear(void);
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#else
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#define post_log_extra(x) do {} while (0)
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#define post_log_path(x) do {} while (0)
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#define post_log_clear() do {} while (0)
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#endif
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/* this function is weak and can be overridden by a mainboard function. */
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void mainboard_post(u8 value);
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void __attribute__ ((noreturn)) die(const char *msg);
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#define __CONSOLE_ENABLE__ \
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((ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE) || \
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ENV_SECMON || \
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ENV_ROMSTAGE || ENV_RAMSTAGE || (ENV_SMM && CONFIG_DEBUG_SMI))
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#if __CONSOLE_ENABLE__
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void console_init(void);
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int console_log_level(int msg_level);
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int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
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void do_putchar(unsigned char byte);
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#define printk(LEVEL, fmt, args...) \
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do { do_printk(LEVEL, fmt, ##args); } while(0)
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#else
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static inline void console_init(void) {}
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static inline int console_log_level(int msg_level) { return 0; }
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static inline void printk(int LEVEL, const char *fmt, ...) {}
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static inline void do_putchar(unsigned char byte) {}
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#endif
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#if CONFIG_CHROMEOS
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/* FIXME: Collision of varargs with AMD headers without guard. */
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#include <console/vtxprintf.h>
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#if __CONSOLE_ENABLE__
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void do_vtxprintf(const char *fmt, va_list args);
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#else
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static inline void do_vtxprintf(const char *fmt, va_list args) {};
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#endif
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#endif
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#endif /* !__ROMCC__ */
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#endif /* CONSOLE_CONSOLE_H_ */
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