coreboot/src/soc/ucb/riscv
Jonathan Neuschäfer 042772a6bd mb/emulation/spike-riscv: Implement mtime_init
This patch lets spike boot to "Payload not loaded" again.

Because soc/ucb/riscv/ does not represent a real SoC, but is a dummy
directory for emulators, and different emulators might have different
memory maps, I moved mtime_init to the mainboard-specific directories
for Spike and QEMU.

Change-Id: I080f7f81df752e25478bd277637bf894bbee4cb2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/28873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-12-05 13:36:26 +00:00
..
cbmem.c riscv: Remove config string support 2017-12-02 05:25:00 +00:00
ipi.c riscv: add support smp_pause / smp_resume 2018-11-05 09:03:40 +00:00
Kconfig riscv: add support smp_pause / smp_resume 2018-11-05 09:03:40 +00:00
Makefile.inc mb/emulation/spike-riscv: Implement mtime_init 2018-12-05 13:36:26 +00:00