erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions
coreboot/src
History
Simon Glass aa58a9eebf spi: Add a way to show SPI transfer speed for reads 
SPI read speed directly impacts boot time and we do quite a lot of
reading.

Add a way to easily find out the speed of SPI flash reads within
coreboot.

Write speed is less important since there are very few writes and they
are small.

BUG=chrome-os-partner:56556
BRANCH=none
TEST=run on gru with SPI_SPEED_DEBUG set to 1. See the output messages:
read SPI 627d4 7d73: 18455 us, 1740 KB/s, 13.920 Mbps

Change-Id: Id3814bd2b7bd045cdfcc67eb1fabc861bf9ed3b2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 82cb93f6be
Original-Change-Id: Iec66f5b8e3ad62f14d836a538dc7801e4ca669e7
Original-Signed-off-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/376944
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Simon Glass <sjg@google.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16701
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06 21:49:25 +02:00
..
acpi
arch x86: acpi: Use GOOG ID for coreboot table 2016-09-27 16:39:30 +02:00
commonlib
console Kconfig: Update default hex values to start with 0x 2016-10-02 19:08:15 +02:00
cpu src/cpu: Remove whitespace after sizeof 2016-10-04 14:32:38 +02:00
device Kconfig: Update default hex values to start with 0x 2016-10-02 19:08:15 +02:00
drivers spi: Add a way to show SPI transfer speed for reads 2016-10-06 21:49:25 +02:00
ec Kconfig: Update default hex values to start with 0x 2016-10-02 19:08:15 +02:00
include cpu/amd/model_fxx: transition away from device_t 2016-10-01 17:39:05 +02:00
lib TPM2: Fill in empty tlcl_resume function in TPM2 tlcl 2016-10-02 19:07:29 +02:00
mainboard google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration 2016-10-06 21:49:06 +02:00
northbridge src/northbridge: Remove unnecessary whitespace 2016-10-04 19:15:55 +02:00
soc rockchip/rk3399: Move big CPU cluster initialization into ramstage 2016-10-06 21:48:50 +02:00
southbridge src/southbridge: Remove unnecessary semicolon 2016-10-04 14:30:52 +02:00
superio sio/winbond/w83627dhg: Add ACPI function to control suspend LED 2016-10-01 22:30:38 +02:00
vboot vboot: clear tpm when required 2016-09-30 03:08:22 +02:00
vendorcode vendorcode/amd/pi/Kconfig: update AGESA_BINARY_PI_LOCATION to hex 2016-10-02 19:08:33 +02:00
Kconfig Kconfig: Update default hex values to start with 0x 2016-10-02 19:08:15 +02:00