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coreboot/src/soc/intel
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Zhixing Ma 30e8fc1f4e soc/intel/alderlake: Fix unknown voltage in SMBIOS 
The current SMBIOS for coreboot is missing processor info for Alder Lake and Raptor Lake SoC, specifically, voltage, max speed,
and upgrade (socket type). This patch implements voltage function.
Refer to SMBIOS spec sheet for documentation:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf

BUG=NONE
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that SMBIOS processor voltage value is correct.

Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I77712b72fa47bdcb56ffddeff15cff9f3b3bbe86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68023
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 15:58:46 +00:00
..
alderlake soc/intel/alderlake: Fix unknown voltage in SMBIOS 2022-10-14 15:58:46 +00:00
apollolake treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk' 2022-10-12 14:18:35 +00:00
baytrail treewide: Use 'fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk' 2022-10-12 14:18:44 +00:00
braswell treewide: Use 'fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk' 2022-10-12 14:18:44 +00:00
broadwell treewide: Use 'fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk' 2022-10-12 14:18:44 +00:00
cannonlake treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk' 2022-10-12 14:18:35 +00:00
common payloads,src: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity 2022-10-13 19:14:57 +00:00
denverton_ns payloads,src: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity 2022-10-13 19:14:57 +00:00
elkhartlake soc/intel: Kconfig: Correct UART source clock value in comment 2022-10-12 23:51:09 +00:00
icelake treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk' 2022-10-12 14:18:35 +00:00
jasperlake treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk' 2022-10-12 14:18:35 +00:00
meteorlake soc/intel: Kconfig: Correct UART source clock value in comment 2022-10-12 23:51:09 +00:00
quark payloads,src: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity 2022-10-13 19:14:57 +00:00
skylake treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk' 2022-10-12 14:18:35 +00:00
tigerlake soc/intel: Kconfig: Correct UART source clock value in comment 2022-10-12 23:51:09 +00:00
xeon_sp payloads,src: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity 2022-10-13 19:14:57 +00:00
Makefile.inc