Angel Pons a93cb11ed6 nb/intel/gm45: Guard macro parameters ... Add brackets around the parameters to avoid operation order problems. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: I023bb116fa2bdcaa7cfdce2445513da3959e827d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45435 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-01-10 23:03:33 +00:00
..
acpi	mb/x/acpi_tables: Rename to mainboard_fill_gnvs()	2021-01-10 11:29:10 +00:00
arch	arch/x86/Makefile.inc: Clean up generated assembly stubs	2021-01-08 08:10:04 +00:00
commonlib	drivers/tpm: Implement full PPI	2020-12-21 02:38:20 +00:00
console	lib/trace: Remove TRACE support	2020-12-02 23:35:58 +00:00
cpu	cpu/intel/haswell/haswell.h: Align with Broadwell	2021-01-10 15:43:10 +00:00
device	device: Add new Kconfig VGA_ROM_RUN_DEFAULT for mainboard user	2021-01-10 17:50:29 +00:00
drivers	ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocations	2021-01-10 11:15:10 +00:00
ec	ec/google/chromeec: add SSFC CBI support	2021-01-08 08:25:42 +00:00
include	soc/intel: Replace acpi_init_gnvs()	2021-01-10 11:39:28 +00:00
lib	arch/x86: Move prologue to .init section	2021-01-07 11:02:03 +00:00
mainboard	mb/intel/adlrvp: Update GPIOs as per latest schematics	2021-01-10 17:49:54 +00:00
northbridge	nb/intel/gm45: Guard macro parameters	2021-01-10 23:03:33 +00:00
security	*/Makefile.inc: Add some INTERMEDIATE targets to .PHONY	2021-01-08 08:08:07 +00:00
soc	soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs	2021-01-10 17:49:19 +00:00
southbridge	sb/intel/bd82x6x: Use PCH_LPC_DEV macro	2021-01-10 15:42:05 +00:00
superio	src/superio: trim and move Makefile.inc, instead use wildcard matches	2020-12-27 14:46:07 +00:00
vendorcode	vc/intel/fsp1_1/skylake: Remove unused header file	2021-01-09 14:45:02 +00:00
Kconfig	Kconfig: Show console debug options if loglevel override is set	2020-12-11 15:58:24 +00:00