This commit introduces support for DDR5 memory configuration on the
PTL RVP DDR5 board. It adds the necessary board ID for PTLP_DDR5_RVP
and integrates a new DDR5 memory configuration within the variant
parameters. The memory configuration includes settings such as
resistor values, sagv values, early command training, and
DDR5-specific training parameters.
Additionally, SPD information retrieval is adapted to accommodate
DDR5-specific settings, such as DIMM module topology and SMBus
addresses.
BUG=none
TEST=Boot to OS with PTL RVP DDR5 board and verify memory
initialization.
Change-Id: I7e3bbb66edcbf4d4a10fcf6899156f125dc3d529
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87179
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
a85b9a21b2