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Felix Held b6bb0c88be vc/amd/fsp/sabrina/platform_descriptor: update DXIO lane mapping table 
Sabrina only supports PCIe and no SATA or 10 GBit/s ethernet on its DXIO
lanes.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib5aa3abf21e20bbe846f1acfdc2755e97eca1e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63121
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-27 15:16:17 +00:00
..
agesa vendorcode/amd/agesa: Add CFLAGS required by CLANG 2022-03-25 20:01:30 +00:00
cimx amd/cimx/sb800: Fix building with clang 2022-03-25 20:13:00 +00:00
fsp vc/amd/fsp/sabrina/platform_descriptor: update DXIO lane mapping table 2022-03-27 15:16:17 +00:00
include
pi vendorcode/amd/pi: Fix building with clang 2022-03-25 20:13:17 +00:00
Kconfig vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles 2020-12-02 17:05:39 +00:00
Makefile.inc