coreboot/src/drivers/intel
Aaron Durbin a56cd048b6 UPSTREAM: drivers/intel/fsp2_0: separate component validation from loading
The current FSP component loading mechanism doesn't handle all the
requirements actually needed. Two things need to be added:
1. XIP support for MemoryInit component
2. Relocating SiliconInit component to not corrupt OS memory.

In order to accommodate those requirements the validation
and header initialization needs to be a separate function.
Therefore, provide fsp_validate_component() to help achieve those
requirements.

BUG=chrome-os-partner:52679
BRANCH=None
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15740
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

Change-Id: I53525498b250033f3187c05db248e07b00cc934d
Reviewed-on: https://chromium-review.googlesource.com/361773
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19 16:31:29 -07:00
..
fsp1_0 UPSTREAM: Fix some cbmem.h includes 2016-06-20 20:09:48 -07:00
fsp1_1 UPSTREAM: drivers/intel/fsp1_1: align on using ACPI_Sx definitions 2016-07-15 08:39:49 -07:00
fsp2_0 UPSTREAM: drivers/intel/fsp2_0: separate component validation from loading 2016-07-19 16:31:29 -07:00
gma intel/gma: Fix VBT generation 2016-04-01 15:34:11 +02:00
i210 UPSTREAM: intel/i210: Change API for function mainboard_get_mac_address() 2016-07-07 01:09:39 -07:00
wifi UPSTREAM: drivers/intel/wifi: Add support for generating SSDT table 2016-06-02 14:06:32 -07:00