coreboot/src
Eric Lai a48e711120 mb/google/deltaur: Correct H1 I2C gpio pin setting
H1 uses I2C3 in the HW schematics and connects to GPP_H6 and GPP_H7.
Previous setting was wrong so correct it.

BUG=b:150165131

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I43c18baea66b927d51689579a40a53f72b94ef36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40487
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20 06:37:32 +00:00
..
acpi src/acpi: Update license headers to SPDX 2020-01-02 14:49:00 +00:00
arch drivers/pc80/rtc: Reorganize prototypes 2020-04-20 06:16:54 +00:00
commonlib src/commonlib: Use SPDX for GPL-2.0-only files 2020-04-04 01:14:24 +00:00
console drivers/pc80/rtc: Drop CMOS_POST_EXTRA option 2020-04-20 06:13:39 +00:00
cpu src/cpu: Use SPDX for GPL-2.0-only files 2020-04-04 14:59:17 +00:00
device drivers/pc80/rtc: Reorganize prototypes 2020-04-20 06:16:54 +00:00
drivers drivers/pc80/rtc: Reorganize prototypes 2020-04-20 06:16:54 +00:00
ec ec/google/chromeec: Update the USBC ACPI device hierarchy 2020-04-17 18:51:04 +00:00
include mmio: Fix failure in bit field macro when accessing >30 bits 2020-04-20 06:20:50 +00:00
lib drivers/pc80/rtc: Reorganize prototypes 2020-04-20 06:16:54 +00:00
mainboard mb/google/deltaur: Correct H1 I2C gpio pin setting 2020-04-20 06:37:32 +00:00
northbridge nb/intel/sandybridge: Refactor get_mem_min_tck 2020-04-19 09:46:42 +00:00
security vboot/secdata: remove retries, readback, and CRC check 2020-04-20 06:06:25 +00:00
soc soc/amd: replace remaining license headers with SPDX ones 2020-04-20 06:33:29 +00:00
southbridge i82371eb: Drop KB/Mouse/FDC declarations 2020-04-18 18:52:34 +00:00
superio Drop unnecessary DEVICE_NOOP entries 2020-04-10 11:25:04 +00:00
vendorcode vc/amd/agesa/f15tn,f16kb: Fix array types 2020-04-18 19:07:19 +00:00
Kconfig src/Kconfig: enable USE_BLOBS by default 2020-04-14 10:03:55 +00:00