coreboot/src
Monika A a47aa776a7 mb/google/brya/variants/trulo: Enable BT audio offload
vGPIO configs are configured to enable SSP2 for BT audio offload.

BUG=b:404741604
Test=Verified BT offload with HDA configuration

Change-Id: Ibce828e32f4640cb234591392bb6ebf0662105fc
Signed-off-by: Monika A <monika.a@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2025-03-20 19:38:34 +00:00
..
acpi src/acpigen: support 0-initialized buffer in acpigen_write_byte_buffer 2025-03-05 16:44:43 +00:00
arch arch/riscv: Add common FDT build 2025-02-14 17:11:19 +00:00
commonlib {commonlib, lib}: Rename CBMEM_ID_FSP_LOGO to CBMEM_ID_BMP_LOGO 2025-03-06 19:02:27 +00:00
console
cpu cpu/intel/haswell: Usee boolean for haswell_is_ult() 2025-03-03 01:15:17 +00:00
device device/pci_device: Move PCI Option ROM code into pci_rom.c 2025-03-10 11:35:57 +00:00
drivers drivers/intel/fsp2_0: Use consistent spacing in BMP color translation 2025-03-19 03:47:22 +00:00
ec ec/google/chromeec: Override Lid State for Factory Netboot 2025-03-13 19:23:00 +00:00
include spd_bin.h: Deduplicate SPD definitions 2025-03-16 05:25:07 +00:00
lib spd_bin.h: Deduplicate SPD definitions 2025-03-16 05:25:07 +00:00
mainboard mb/google/brya/variants/trulo: Enable BT audio offload 2025-03-20 19:38:34 +00:00
northbridge haswell NRI: Do sense amplifier offset training 2025-03-08 22:55:39 +00:00
sbom
security
soc Revert "soc/mediatek/mt8196: Delay 0.5ms after enabling PMIF SPMI SW interface" 2025-03-19 08:13:30 +00:00
southbridge haswell NRI: Add DDR3 JEDEC reset and init 2025-03-08 22:53:24 +00:00
superio
vendorcode Revert "soc/intel/jasperlake: Add CrashLog implementation for Intel JSL" 2025-03-17 20:21:04 +00:00
Kconfig Kconfig: Update prompt and help text for CBFS_SIZE 2025-03-01 23:29:09 +00:00