Youness Alaoui a462c157f8 purism/librem13: Fix M.2 issues. ... The M.2 SSD is on the SATA port 3, which also required the DTLE setting to be set. This fixes issues with the M.2 SSD not being detected/stable. Change-Id: Id39d9ec395a2d9d32be4c079678d0708f08b3935 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/18409 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>		2017-02-22 22:25:24 +01:00
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acpi	src/acpi: Capitalize ACPI and SATA	2016-07-31 19:25:40 +02:00
arch	arch/x86/acpigen: Provide helper functions for enabling/disabling GPIO	2017-02-22 22:19:29 +01:00
commonlib	buildsystem: Drop explicit (k)config.h includes	2016-12-08 19:46:53 +01:00
console	console: Enable do_printk_va_list for VBOOT	2016-12-27 18:07:39 +01:00
cpu	src/cpu/x86: Update/Add license headers to all files	2017-02-22 22:23:11 +01:00
device	device: Add scan_generic_bus support	2017-02-16 08:41:52 +01:00
drivers	acpi: Add ACPI_ prefix to IRQ enum and struct names	2017-02-22 22:19:19 +01:00
ec	ec/lenovo: Add guards to fix build errors without SMBIOS	2017-02-20 04:46:49 +01:00
include	arch/x86: add functions to generate random numbers	2017-02-20 04:46:10 +01:00
lib	ddr3 spd: move accessor code into lib/spd_bin.c	2017-02-10 18:04:33 +01:00
mainboard	purism/librem13: Fix M.2 issues.	2017-02-22 22:25:24 +01:00
northbridge	southbridge/amd: Add LPC bridge acpi path for Family14 and SB800	2017-02-22 01:03:23 +01:00
soc	Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and 3.	2017-02-22 22:24:50 +01:00
southbridge	southbridge/amd: Add LPC bridge acpi path for Family14 and SB800	2017-02-22 01:03:23 +01:00
superio	sio/ite/it8783ef: Return (0) in ACPI _PSC methods	2016-12-13 22:49:24 +01:00
vboot	build system: mark sub-make invocations as parallelizable	2017-01-31 18:51:55 +01:00
vendorcode	AGESA: Remove nonexistent include path	2017-02-14 10:57:45 +01:00
Kconfig	src/Kconfig: Move bootblock behavior to arch/x86 as TODO suggested	2017-02-14 19:03:42 +01:00