coreboot/src/device
Lee Leahy e1ba3dac41 device: Add class and subclass name support
Add support to display class and subclass names for PCI devices.

BRANCH=none
BUG=None
TEST=Build and run on strago/cyan.

Change-Id: I5136fae45b8a1cd02541f233d29a246cdfcd8331
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a7c9b0d7201b09a06ea32f0db84187d15f767c80
Original-Change-Id: Ibf2ee89dd84040ca6ab0e52857a69f7ed0c28f37
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/263342
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/9901
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 08:55:29 +02:00
..
dram cbfs: correct types used for accessing files 2015-04-01 22:51:10 +02:00
oprom Unify byte order macros and clrsetbits 2015-04-21 08:23:25 +02:00
azalia_device.c
cardbus_device.c
cpu_device.c
device.c device: convert to stopwatch API 2015-03-21 17:00:40 +01:00
device_romstage.c
device_util.c AMD fam10: Drop PCI_BUS_SEGN_BITS 2015-03-09 19:33:08 +01:00
hypertransport.c
Kconfig PCIe: Add L1 Sub-State support. 2015-03-23 13:11:15 +01:00
Makefile.inc device: Add class and subclass name support 2015-04-22 08:55:29 +02:00
pci_class.c device: Add class and subclass name support 2015-04-22 08:55:29 +02:00
pci_device.c AMD fam10: Drop PCI_BUS_SEGN_BITS 2015-03-09 19:33:08 +01:00
pci_early.c
pci_ops.c
pci_rom.c
pciexp_device.c PCIe: Revise L1 Sub-State support 2015-03-23 13:11:18 +01:00
pcix_device.c
pnp_device.c
root_device.c
smbus_ops.c
software_i2c.c device: convert to stopwatch API 2015-03-21 17:00:40 +01:00