coreboot/src
Aaron Durbin a3cecb2e71 drivers/intel/fsp2_0: add option to incorporate platform memory version
On Chrome OS systems a memory setting change is needed to be deployed
without updating the FSP blob proper. Under such conditions one needs
to trigger retrain of the memory. For ease of use provide an option,
FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS, which incorproates the SoC
and mainboard memory setting version number into the FSP version
passed to the platform. The lower 8 bits of the FSP version are the
build number which in practice is normally 0. Use those 8 bits to
include the SoC and mainboard memory settings version. When FSP,
SoC, or mainboard memory setting number is bumped a retrain will be
triggered.

BUG=b:37687843

Change-Id: I6a269dcf654be7a409045cedeea3f82eb641f1d6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19452
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-04-28 15:56:49 +02:00
..
acpi src/acpi: Capitalize ACPI and SATA 2016-07-31 19:25:40 +02:00
arch arch/x86: Add read64 and write64 functions 2017-04-25 06:14:39 +02:00
commonlib include: Add xmalloc, xzmalloc and dma routines 2017-04-25 00:52:03 +02:00
console console: rework log level to not be reliant on ROMSTAGE_CONST 2017-04-25 18:13:56 +02:00
cpu nb/amd/amdk8: Link raminit_f.c 2017-04-27 10:18:28 +02:00
device x86/acpi: Use initialized VBIOS in VFCT table 2017-04-27 18:17:57 +02:00
drivers drivers/intel/fsp2_0: add option to incorporate platform memory version 2017-04-28 15:56:49 +02:00
ec ec/roda/it8518: Do EC write manually with long timeout 2017-04-08 13:17:56 +02:00
include AMD Geode: Move conflicting mainboard_romstage_entry() 2017-04-25 22:39:05 +02:00
lib cbmem_console: Document known reimpementations of console structure/API 2017-04-26 01:31:51 +02:00
mainboard google/gru: tpm on bob: cr50: add irq clear/irq status for tpm irq 2017-04-28 06:49:18 +02:00
northbridge cpu/amd/pi: Change wrapper to use config option 2017-04-27 18:52:00 +02:00
soc rockchip: gpio: add gpio_input_irq & gpio_irq_status 2017-04-28 06:49:01 +02:00
southbridge amd/pi/hudson: Add VBNV cmos reset option 2017-04-27 17:09:08 +02:00
superio superio/fintek: Add support for Fintek F71808A 2017-03-27 19:19:56 +02:00
vboot Remove libverstage as separate library and source file class 2017-03-28 22:18:53 +02:00
vendorcode Kconfig: provide MAINBOARD_HAS_TPM_CR50 option 2017-04-24 22:02:55 +02:00
Kconfig include: Add xmalloc, xzmalloc and dma routines 2017-04-25 00:52:03 +02:00