coreboot/src
Aaron Durbin a3a06aeac5 drivers/intel/fsp2_0: fix hand-off-block types and size
The gcc compiler treats sizeof(void) == 1. Therefore requesting
a 1 byte reservation in cbmem and writing a pointer into the
buffer returned is wrong. Fix the size of the request to be
32-bits because FSP 2.0 is in 32-bit space by definition. Also,
since the access to the field happens across stage boundaries
it's important to ensure fixed widths are used in case a later
stage has a different pointer bit width.

BUG=chrome-os-partner:52679

Change-Id: Ib4efc7d5369d44a995318aac6c4a7cfdc73e4a8c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15737
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-19 20:14:10 +02:00
..
acpi arch/x86: provide common Intel ACPI hardware definitions 2016-07-15 08:31:21 +02:00
arch arch/riscv: Remove enter_supervisor 2016-07-18 22:51:13 +02:00
commonlib commonlib: fix 'AFTER CAR' spacing to align with others 2016-07-19 20:13:38 +02:00
console console/post: be explicit about conditional cmos_post_log() compiling 2016-05-25 18:04:11 +02:00
cpu AMD binaryPI: Use common romstage ram stack 2016-07-15 12:31:07 +02:00
device device: i2c: Add support for I2C bus operations 2016-06-09 17:05:40 +02:00
drivers drivers/intel/fsp2_0: fix hand-off-block types and size 2016-07-19 20:14:10 +02:00
ec ec/google/chromeec: provide common SMI handler helpers 2016-07-15 08:35:29 +02:00
include lib: add poweroff() declaration 2016-07-15 08:35:15 +02:00
lib lib: provide memrange library in romstage 2016-07-19 20:13:20 +02:00
mainboard mainboard/google/reef: explicitly set shipping Chrome OS options 2016-07-19 20:13:08 +02:00
northbridge nb/intel/x4x: Fix CAS latency detection 2016-07-19 18:55:50 +02:00
soc soc/intel/apollolake: remove unused FIT_POINTER define 2016-07-19 20:13:55 +02:00
southbridge southbridge/intel/fsp_bd82x6x: use common Intel ACPI hardware definitions 2016-07-15 08:34:46 +02:00
superio sio/winbond/w83667hg-a: Add pinmux defines for UART B 2016-05-29 19:34:54 +02:00
vendorcode chromeos: Fill in the firmware id (RO, RW A, RW B) FMAP sections 2016-07-15 00:40:19 +02:00
Kconfig Romstage spinlocks require EARLY_CBMEM_INIT 2016-07-10 04:03:31 +02:00