coreboot/src
Lijian Zhao a31872c615 ec/google/wilco: Turn on wake up from lid
Send required EC command to enable ACPI S3 wake up from lid switch.

BUG=b:120748824
TEST=Put Sarien system into S3 and then wake up from lid switch
successful.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I13f3469847b0886147b8b624311a1ece796f847b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-24 22:03:32 +00:00
..
acpi
arch riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV 2019-01-24 14:21:01 +00:00
commonlib buildsystem: Promote rules.h to default include 2019-01-16 11:51:07 +00:00
console console/init: Print log level in coreboot banner 2019-01-17 13:19:53 +00:00
cpu cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR 2019-01-24 13:42:36 +00:00
device device/pci_device: Do not break tree topology 2019-01-10 12:47:18 +00:00
drivers drivers/generic/gpio_keys: Add trigger for wakeup event action 2019-01-24 13:54:51 +00:00
ec ec/google/wilco: Turn on wake up from lid 2019-01-24 22:03:32 +00:00
include cbmem_top: Fix comment and remove upper limit 2019-01-24 13:54:21 +00:00
lib lib/boot_device: Add API for write protect a region 2019-01-21 13:25:46 +00:00
mainboard mb/*/*/devicetree.cb: Move the ioapic device under the LPC bridge 2019-01-24 21:46:51 +00:00
northbridge nb/intel/x4x: Put stage cache in TSEG 2019-01-24 13:44:14 +00:00
security tss/tcg-2.0: remove unnecessary break from marshaling code 2019-01-17 13:19:47 +00:00
soc Revert "soc/intel/denverton_ns: Rewrite pmutil using pmclib" 2019-01-24 15:23:47 +00:00
southbridge sb/intel/common: More SMBus block_cmd_loop() 2019-01-24 13:38:27 +00:00
superio superio/ite: Add it8528e 2019-01-24 09:10:13 +00:00
vendorcode vendorcode/{amd,cavium,intel}: Remove trailing whitespace 2019-01-17 14:52:33 +00:00
Kconfig [RFC]util/checklist: Remove this functionality 2019-01-14 19:42:59 +00:00