coreboot/src
Duncan Laurie a187695c51 lynxpoint: Enable extra 16 IOAPIC entries for GPIO PIRQ
LynxPoint-LP has an additional 16 entries in the IOAPIC that
can be assigned to specific GPIOs when they are configured
as PIRQ.

The maximum redirection entries field in the IOAPIC needs to
be set to 0x27 when this is enabled.

Additionally specific GPIOs need to be routed to PIRQ so they
interrupt via the IOAPIC instead of the GPIO IRQ 14/15.

BUG=chrome-os-partner:19664
BRANCH=none
TEST=manual: nothing specific changes with this commit, but
it is used with a series of commits to enable the trackpad
interrupt on slippy.

Change-Id: Ie587e1d203422ff6fb7fc5056d20a5ae66720991
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56620
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2013-05-24 16:27:42 -07:00
..
arch smbios: Add generic type41 write function 2013-05-24 14:02:57 -07:00
console console: Make use of CONFIG_USE_OPTION_TABLE 2013-04-01 20:54:48 +02:00
cpu exynos5420: Replace the 5250 clock logic with 5420. 2013-05-22 04:53:51 -07:00
device device tree: track init times 2013-05-01 15:36:25 -07:00
drivers elog: Check for successful flash erase in elog_shrink 2013-05-24 14:02:57 -07:00
ec ec: Remove hardcoded GPI offset in EC SCI 2013-05-21 11:18:56 -07:00
include smbios: Add generic type41 write function 2013-05-24 14:02:57 -07:00
lib BACKPORT: cbmem console: use cache-as-ram API and cleanup 2013-05-16 15:06:26 -07:00
mainboard wtm2: add ssdt2 table 2013-05-24 14:02:59 -07:00
northbridge haswell: update pei_data data structure 2013-05-24 11:36:49 -07:00
southbridge lynxpoint: Enable extra 16 IOAPIC entries for GPIO PIRQ 2013-05-24 16:27:42 -07:00
superio Drop prototype guarding for romcc 2013-05-10 11:55:20 -07:00
vendorcode BACKPORT: chromeos: use cache-as-ram migration API for vbnv 2013-05-16 15:06:25 -07:00
Kconfig BACKPORT: x86: add thread support 2013-05-15 11:19:50 -07:00