Hung-Te Lin a01f8bc450 soc/mediatek: a common implementation to register BL31 reset ... The implementations of register_reset_to_bl31() are the same for MedaiTek platforms, so we extract them to soc/common/bl31.c. BUG=None TEST=build pass Change-Id: I297ea2e18a6d7e92236cf415844b166523616bdf Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>		2022-09-07 09:20:25 +00:00
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variants/dojo	mb/google/cherry: Add PCIe domain support for dojo	2022-03-30 14:59:55 +00:00
board_info.txt
boardid.c
bootblock.c	mb/google/cherry: Pre-initialize PCIe at the bootblock stage	2022-03-29 15:41:43 +00:00
chromeos.c
chromeos.fmd	treewide: Unify Google branding	2022-07-04 14:02:26 +00:00
devicetree.cb
gpio.h
Kconfig	tpm: Refactor TPM Kconfig dimensions	2022-04-21 23:07:20 +00:00
Kconfig.name
mainboard.c	soc/mediatek: a common implementation to register BL31 reset	2022-09-07 09:20:25 +00:00
Makefile.inc
memlayout.ld
regulator.c	mb/google: Use boolean type for "enable" argument for regulator	2022-07-21 10:33:22 +00:00
reset.c
romstage.c
sdram_configs.c