coreboot/src
Vadim Bendebury 9ed93cb5d5 gru: kevin: configure board GPIOs
Set board GPIOs as required and add their description into the
appropriate section of the coreboot table, to make them available to
depthcharge.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to use
     keyboard on Gru, which indicates that the EC interrupt GPIO is
     properly configured. The rest of the pins will be verified later.

Change-Id: I5818bfe855f4e7faa2114484a9b7b44c7d469727
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: e02a05f
Original-Change-Id: I82be76bbd3211179e696526a34cc842cb1987e69
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346631
Reviewed-on: https://review.coreboot.org/15031
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08 23:21:55 +02:00
..
acpi acpi/: add missing license header 2016-01-14 22:52:11 +01:00
arch SMBIOS: Implement SKU field 2016-06-02 06:24:24 +02:00
commonlib commonlib/lz4: Avoid unaligned memory access on RISC-V 2016-05-31 21:07:03 +02:00
console console/post: be explicit about conditional cmos_post_log() compiling 2016-05-25 18:04:11 +02:00
cpu AGESA vendorcode: Build a common amdlib 2016-05-18 10:44:43 +02:00
device device: Add an ACPI device name and path concept to devices 2016-05-21 05:59:52 +02:00
drivers drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h header 2016-06-08 22:35:18 +02:00
ec chromeec: Move EC image hash to separate file in CBFS 2016-06-03 17:24:26 +02:00
include SMBIOS: Implement SKU field 2016-06-02 06:24:24 +02:00
lib cbfs: Use NO_XIP_EARLY_STAGES to decide if stage is XIP 2016-06-02 17:21:39 +02:00
mainboard gru: kevin: configure board GPIOs 2016-06-08 23:21:55 +02:00
northbridge nb/intel/x4x: Fix unpopulated value 2016-06-04 23:46:05 +02:00
soc gru: kevin: configure board GPIOs 2016-06-08 23:21:55 +02:00
southbridge drivers/lenovo: Add hybrid graphics driver 2016-06-01 23:22:01 +02:00
superio sio/winbond/w83667hg-a: Add pinmux defines for UART B 2016-05-29 19:34:54 +02:00
vendorcode AGESA boards: Split dispatcher to romstage and ramstage 2016-06-04 23:44:33 +02:00
Kconfig Add Board Checklist Support 2016-06-03 17:29:13 +02:00