Michał Żygowski 9ec60411ac soc/intel/elkhartlake/romstage/fsp_params.c: separate debug params ... This commit separates setting FSP debug params from the rest of code and configures FSP serial port parameters. Other ports (0x3E8 and 0x2E8) are omitted since Elkhart Lake FSP only supports 0x3F8 and 0x2F8. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I84f7c19a7c2fd5a4db18f5a37e1c667da017aace Reviewed-on: https://review.coreboot.org/c/coreboot/+/72404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>		2023-02-27 16:45:36 +00:00
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amd	soc/amd/common/fsp/dmi.c: Fill in mem manufacturer from CBI	2023-02-27 16:40:57 +00:00
cavium	treewide: Remove duplicated include <device/pci.h>	2023-02-01 03:03:34 +00:00
example/min86	soc: Add SPDX license headers to Makefiles	2022-10-31 03:27:13 +00:00
intel	soc/intel/elkhartlake/romstage/fsp_params.c: separate debug params	2023-02-27 16:45:36 +00:00
mediatek	soc/mediatek: Add "DRAM" to Kconfig MEDIATEK_BLOB_FAST_INIT name	2023-02-23 12:14:47 +00:00
nvidia	treewide: stop calling custom TPM log "TCPA"	2023-01-11 16:00:55 +00:00
qualcomm	Revert "soc/qualcomm: Increase SPI frequency to 75 MHz"	2023-02-24 19:28:24 +00:00
rockchip	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00
samsung	treewide: Fix old-style declarations	2023-01-17 04:23:49 +00:00
sifive/fu540	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00
ti	src/soc/ti: Remove unnecessary space after casts	2022-11-22 13:42:28 +00:00
ucb/riscv	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00