Michał Żygowski 9ec479de47 soc/intel/alderlake/meminit.c: Guard CsPiStartHighinEct properly ... Build issue introduced by patch CB:76418 (commit hash 01025d3ae7) for Google boards. Patch has not been rebased to latest master and tested before submission causing the Jenkins jobs to fail. Change-Id: I95bd2485b98be4ab3a39eaaebb9efb34db93bbe8 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76915 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2023-08-03 11:19:13 +00:00
..
amd	soc/amd/mendocino: select SOC_AMD_COMMON_BLOCK_CPU_SYNC_PSP_ADDR_MSR	2023-08-01 17:57:18 +00:00
cavium	soc/cavium/cn81xx: Use correct size for MPIDR_EL1 register	2023-05-13 17:22:16 +00:00
example/min86
intel	soc/intel/alderlake/meminit.c: Guard CsPiStartHighinEct properly	2023-08-03 11:19:13 +00:00
mediatek	soc/mediatek/common/dsi: Add actual values to the log messages	2023-07-14 03:11:53 +00:00
nvidia	treewide: stop calling custom TPM log "TCPA"	2023-01-11 16:00:55 +00:00
qualcomm	treewide: Remove 'extern' from functions declaration	2023-05-26 13:45:24 +00:00
rockchip
samsung	treewide: Fix old-style declarations	2023-01-17 04:23:49 +00:00
sifive/fu540	soc/sifive: Comment out set but unused variables	2023-06-04 19:22:50 +00:00
ti
ucb/riscv