coreboot/src/cpu
Patrick Rudolph a1f82532f2 cpu/x86/64bit: Back up/restore CR3 on mode switch
Store CR3 on stack and restore it when returning from protected
mode call, since the stage might have set up different page tables
than the default ones linked into all stages.

Tested: intel/archercity still boots to payload in x86_64.

Change-Id: If94a24925994ac9599be24f6454ea28d02ff0c67
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2025-01-08 08:18:21 +00:00
..
amd treewide: Remove unused CHIPs 2024-02-20 11:01:36 +00:00
armltd arch to cpu: Add SPDX license headers to Kconfig files 2024-02-18 01:58:52 +00:00
intel cpu/intel/car/romstage: Fix false-positive stack corruption 2024-12-17 17:36:47 +00:00
power9 include/device/device.h: Remove CHIP_NAME() macro 2024-01-31 09:51:58 +00:00
qemu-power8 include/device/device.h: Remove CHIP_NAME() macro 2024-01-31 09:51:58 +00:00
qemu-x86 cpu/qemu: Enable IDT_IN_EVERY_STAGE 2024-12-17 17:37:54 +00:00
via cpu/via/c7: Compress ramstage with LZ4 by default 2024-11-21 09:26:17 +00:00
x86 cpu/x86/64bit: Back up/restore CR3 on mode switch 2025-01-08 08:18:21 +00:00
Kconfig arch to cpu: Add SPDX license headers to Kconfig files 2024-02-18 01:58:52 +00:00
Makefile.mk via: Start template for VIA C7 w/ CX700 northbridge 2024-11-11 09:16:55 +00:00