coreboot/src/soc
Nico Huber 9ea70c02cd intel/cannonlake: Implement PCIe RP devicetree update
Some existing devicetrees were manually adapted to anticipate
root-port switching. Now, their PCI-device on/off settings should
just reflect the `PcieRpEnable` state and configuration happens
on the PCI function that was assigned at reset.

Change-Id: I4d76f38c222b74053c6a2f80b492d4660ab4db6d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-26 15:01:00 +00:00
..
amd soc/amd/picasso: Give the mainboard the ability to modify the MADT table 2020-05-26 14:37:22 +00:00
cavium src: Remove leading blank lines from SPDX header 2020-05-18 07:00:27 +00:00
intel intel/cannonlake: Implement PCIe RP devicetree update 2020-05-26 15:01:00 +00:00
mediatek soc/mediatek/mt8183: Set CA and DQ vref range to correct value 2020-05-20 09:50:45 +00:00
nvidia src: Remove leading blank lines from SPDX header 2020-05-18 07:00:27 +00:00
qualcomm src: Remove unused 'include <string.h>' 2020-05-18 07:41:24 +00:00
rockchip src: Remove leading blank lines from SPDX header 2020-05-18 07:00:27 +00:00
samsung samsung/exynos5420: add resources during read_resources() 2020-05-14 21:27:34 +00:00
sifive src: Remove leading blank lines from SPDX header 2020-05-18 07:00:27 +00:00
ucb treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00