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coreboot/src/include/cpu/intel
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Felix Zimmer 9d878fc6c0 soc/intel/xeon_sp: Add support for Emerald Rapids (5th Gen Xeon-SP) CPUs 
TEST=build/boot ASRock SPC741D8-2L2T/BCM with Intel Xeon Silver 4514Y to
edk2 and Linux 6.12

Change-Id: Iefe3228dcf3626aa9a72d16a288751af47d526f6
Signed-off-by: Felix Zimmer <felix.zimmer@student.kit.edu>
Co-authored-by: Yussuf Khalil <yussuf.khalil@kit.edu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2025-05-21 17:10:46 +00:00
..
cpu_ids.h soc/intel/xeon_sp: Add support for Emerald Rapids (5th Gen Xeon-SP) CPUs 2025-05-21 17:10:46 +00:00
em64t100_save_state.h src/include: Drop unneeded empty lines 2020-09-14 07:09:41 +00:00
em64t101_save_state.h src/include: Drop unneeded empty lines 2020-09-14 07:09:41 +00:00
fsb.h treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
l2_cache.h src: Remove unnecessary semicolons from the end of macros 2023-11-10 15:27:45 +00:00
microcode.h cpu/intel/microcode: Have API to re-load microcode patch 2022-06-22 12:35:53 +00:00
msr.h soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE 2025-03-10 15:19:26 +00:00
post_codes.h src/*/post_code.h: Change post code prefix to POSTCODE 2023-08-05 16:04:46 +00:00
smm_reloc.h mb/emulation/qemu-q35: Split smm_close() and smm_lock() 2022-11-17 07:42:55 +00:00
speedstep.h cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm 2022-12-05 14:22:12 +00:00
turbo.h treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00