coreboot/src/southbridge
Uwe Hermann d436a4b4bc Correct the RAM checking code to _not_ check the range from 640 KB - 1 MB,
as that is not RAM but used for other stuff.

First try at PCI init added to src/mainboard/tyan/s1846/Config.lb.

Use a real payload (FILO) per default now.

Note: this cannot boot a payload, yet, but it gets a lot further now.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-03 08:50:37 +00:00
..
amd Use the canonical name of the vendors/devices and the 2006-11-05 18:50:49 +00:00
broadcom Use the canonical name of the vendors/devices and the 2006-11-05 18:50:49 +00:00
intel Correct the RAM checking code to _not_ check the range from 640 KB - 1 MB, 2007-05-03 08:50:37 +00:00
nvidia Fix some CHIP_NAME() entries to use canonical names. 2007-02-19 19:11:20 +00:00
ricoh/rl5c476 Fix epia-m build after u8/u16/u32 changes in Yh Lu's patch. 2007-04-07 09:17:00 +00:00
via Add initial pre-RAM serial output support for the VIA VT82C686(A/B) 2007-03-17 14:00:23 +00:00
winbond/w83c553 Updating FSF address in the code. 2005-10-05 18:17:45 +00:00