4de1a31cb0
With chipset_power_state filled in romstage CBMEM hooks and GNVS allocated early in ramstage, GNVS wake source is now also filled for normal boot path. Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
107 lines
2.2 KiB
C
107 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi_gnvs.h>
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#include <acpi/acpigen.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <soc/nvs.h>
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#include <stdint.h>
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#include <string.h>
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#include <types.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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static struct global_nvs *gnvs;
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void acpi_create_gnvs(void)
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{
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size_t gnvs_size;
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gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
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if (gnvs)
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return;
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/* Match with OpRegion declared in global_nvs.asl. */
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gnvs_size = sizeof(struct global_nvs);
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if (gnvs_size < 0x100)
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gnvs_size = 0x100;
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if (CONFIG(ACPI_HAS_DEVICE_NVS))
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gnvs_size = 0x2000;
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else if (CONFIG(CHROMEOS))
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gnvs_size = 0x1000;
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gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, gnvs_size);
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if (!gnvs)
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return;
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memset(gnvs, 0, gnvs_size);
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if (CONFIG(CONSOLE_CBMEM))
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gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
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if (CONFIG(CHROMEOS))
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gnvs_assign_chromeos((u8 *)gnvs + GNVS_CHROMEOS_ACPI_OFFSET);
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}
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void *acpi_get_gnvs(void)
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{
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if (gnvs)
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return gnvs;
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gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
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if (gnvs)
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return gnvs;
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printk(BIOS_ERR, "Unable to locate Global NVS\n");
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return NULL;
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}
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void *acpi_get_device_nvs(void)
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{
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return (u8 *)gnvs + GNVS_DEVICE_NVS_OFFSET;
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}
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/* Implemented under platform. */
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__weak void soc_fill_gnvs(struct global_nvs *gnvs_) { }
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__weak void mainboard_fill_gnvs(struct global_nvs *gnvs_) { }
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/* Called from write_acpi_tables() only on normal boot path. */
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void acpi_fill_gnvs(void)
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{
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if (!gnvs)
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return;
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soc_fill_gnvs(gnvs);
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mainboard_fill_gnvs(gnvs);
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acpigen_write_scope("\\");
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acpigen_write_name_dword("NVB0", (uintptr_t)gnvs);
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acpigen_write_name_dword("NVS0", 0x100);
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acpigen_pop_len();
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if (CONFIG(CHROMEOS)) {
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acpigen_write_scope("\\");
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acpigen_write_name_dword("NVB2", (uintptr_t)gnvs + GNVS_CHROMEOS_ACPI_OFFSET);
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acpigen_write_name_dword("NVS2", 0xf00);
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acpigen_pop_len();
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}
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if (CONFIG(ACPI_HAS_DEVICE_NVS)) {
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acpigen_write_scope("\\");
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acpigen_write_name_dword("NVB1", (uintptr_t)gnvs + GNVS_DEVICE_NVS_OFFSET);
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acpigen_write_name_dword("NVS1", 0x1000);
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acpigen_pop_len();
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}
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}
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int acpi_reset_gnvs_for_wake(struct global_nvs **gnvs_)
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{
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if (!gnvs)
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return -1;
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/* Set unknown wake source */
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gnvs->pm1i = -1;
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gnvs->gpei = -1;
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*gnvs_ = gnvs;
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return 0;
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}
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