Marc Jones 9afc5c05f0 baytrail: Switch from ACPI mode to PCI mode for legacy support ... Most Baytrail based devices MMIO registers are reported in ACPI space and the device's PCI config space is disabled. The PCI config space is required for many "legacy" OSs that don't have the ACPI driver loading mechanism. Depthcharge signals the legacy boot path via the SMI 0xCC and the coreboot SMI handler can switch the device specific registers to re-enable PCI config space. BUG=chrome-os-partner:30836 BRANCH=None TEST=Build and boot Rambi SeaBIOS. Change-Id: I87248936e2a7e026f38c147bdf0df378e605e370 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: dbb9205ee2 Original-Change-Id: Ia5e54f4330eda10a01ce3de5aa4d86779d6e1bf9 Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219801 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Mike Loptien <mike.loptien@se-eng.com> Original-Tested-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/9459 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>		2015-04-10 19:21:49 +02:00
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amd	AMD: Uniformly define MSRs for TOP_MEM and TOP_MEM2	2015-03-07 21:22:20 +01:00
intel	acpi: Generate valid ACPI processor objects	2015-02-16 21:02:30 +01:00
x86	baytrail: Switch from ACPI mode to PCI mode for legacy support	2015-04-10 19:21:49 +02:00
cpu.h	cpu/cpu.h: Allow compiling with __SIMPLE_DEVICE__	2014-01-06 09:47:01 +01:00