coreboot/src/include/cpu/intel
Arthur Heymans 98c92570d9 cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.

This removes the need for a magic lapic in the devicetree.

Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-05 14:22:12 +00:00
..
cpu_ids.h soc/intel/cnl: Add Cometlake-H/S Q0 (10+2) CPU ID 2022-09-16 16:17:36 +00:00
em64t100_save_state.h src/include: Drop unneeded empty lines 2020-09-14 07:09:41 +00:00
em64t101_save_state.h src/include: Drop unneeded empty lines 2020-09-14 07:09:41 +00:00
fsb.h treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
l2_cache.h src/include: Add missing includes 2020-07-26 21:37:35 +00:00
microcode.h cpu/intel/microcode: Have API to re-load microcode patch 2022-06-22 12:35:53 +00:00
msr.h soc/intel/car: Add support for bootguard CAR 2021-06-22 13:15:09 +00:00
post_codes.h cpu/intel/car: Define post codes 2022-11-23 03:47:18 +00:00
smm_reloc.h mb/emulation/qemu-q35: Split smm_close() and smm_lock() 2022-11-17 07:42:55 +00:00
speedstep.h cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm 2022-12-05 14:22:12 +00:00
turbo.h treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00