coreboot/src
Alexandru Gagniuc 986349df64 vendorcode/amd/agesa/fam15tn: Clean #includes in public headers
Right now, coreboot code using AGESA headers can only build if all the
AGESA path are given to the compiler via the "-I" option. This is sub-
optimal, as it requires us to have every AGESA source directory
specified as a compiler include path. This pollutes our global include
paths.

We restrict the compiler include paths to only allow "AGESA_ROOT/" and
"AGESA_ROOT/Include". We then modify the AGESA headers to specify
non-local include files relative to "AGESA_ROOT/Include".

We use the convention that includes relative to the directory of the
header are included as "path/to/header.h", while includes relative to
AGESA_ROOT are included as <path/to/header.h>.

This change allows building coreboot code based on AGESA with the
limited subset of include paths, but does not allow AGESA itself to
build with this restricted subset.

Change-Id: I31102273c8caa8d6b1d80774bfd35711825bec03
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5424
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-06 05:43:20 +01:00
..
arch x86: Update the check for Forbidden global variables 2014-12-05 09:20:41 +01:00
console ipq8064: prepare UART driver for use in coreboot 2014-12-05 20:22:47 +01:00
cpu FSP platform microcode: Update to remove Kconfig variable 2014-12-05 21:40:12 +01:00
device device/dram/ddr3.c: Fix sizeof on array func param overflow 2014-11-08 07:09:34 +01:00
drivers FSP platform microcode: Update to remove Kconfig variable 2014-12-05 21:40:12 +01:00
ec Replace hlt with halt() 2014-12-02 10:25:55 +01:00
include Replace hlt() loops with halt() 2014-11-30 12:20:07 +01:00
lib ipq8064: prepare UART driver for use in coreboot 2014-12-05 20:22:47 +01:00
mainboard mainboard/lenovo/g505s/buildOpts.c: Trivial variable rename 2014-12-06 03:25:52 +01:00
northbridge drivers/intel/fsp: add upd macros and #defines 2014-12-05 16:19:45 +01:00
soc fsp_baytrail: Update function disable code 2014-12-05 22:02:04 +01:00
southbridge southbridge/hudson: Disable USB controllers if devicetree says so 2014-12-06 02:47:18 +01:00
superio Mark non-executable files non-executable 2014-12-01 17:33:07 +01:00
vendorcode vendorcode/amd/agesa/fam15tn: Clean #includes in public headers 2014-12-06 05:43:20 +01:00
Kconfig Add UCB RISCV support for architecture, soc, and emulation mainboard.. 2014-12-01 19:06:43 +01:00