Raul E Rangel 0d6972fcb2 vc/amd/cezanne: Add support to map UARTs ... This will allow coreboot to directly write to the UART controller. BUG=b:215599230 TEST=Try mapping the uart on guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibd346cec2994e612f2901bb91d572982ce2ed5e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>		2022-02-07 14:07:41 +00:00
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amd	vc/amd/cezanne: Add support to map UARTs	2022-02-07 14:07:41 +00:00
cavium	src: use ARRAY_SIZE where possible	2021-02-15 11:30:40 +00:00
eltan	src/vendorcode/eltan: Don't reference CONFIG_CBFS_SIZE	2021-07-28 08:19:30 +00:00
google	chromeos: Add an elog for Chrome OS diagnostic boot	2022-01-11 23:44:51 +00:00
intel	vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04	2022-01-13 18:04:13 +00:00
mediatek	vc/mediatek/mt8195: Fix rank1 CKE setting for single-rank DRAM	2021-12-01 09:48:17 +00:00
siemens	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
Makefile.inc	soc/mediatek/mt8192: initialize DRAM using vendor reference code	2021-03-08 03:15:43 +00:00