Arthur Heymans 93cb1809a2 cpu/intel/socket_LGA775: Align CAR DCACHE_RAM_BASE to SIZE ... This fixes a regression introduced by Commit 985821c (cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE) where the CAR base is not aligned to its size. Change-Id: If54cb178e86426e1491dda4047302632d876a8f0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50029 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-01-28 12:34:52 +00:00
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amd	cpu/amd/agesa/family15tn/fixme.c	2021-01-28 09:17:40 +00:00
armltd	Kconfig: comply to Linux 5.3's Kconfig language rules	2019-11-23 20:09:56 +00:00
intel	cpu/intel/socket_LGA775: Align CAR DCACHE_RAM_BASE to SIZE	2021-01-28 12:34:52 +00:00
qemu-power8	src: Remove leading blank lines from SPDX header	2020-05-18 07:00:27 +00:00
qemu-x86	mb/emulation/qemu: Copy page tables to DRAM in assembly	2021-01-11 07:34:19 +00:00
x86	arch/x86: Top-align .init in bootblock	2021-01-28 08:54:21 +00:00
Kconfig	arch/x86: Implement RESET_VECTOR_IN_RAM	2020-04-29 05:38:00 +00:00
Makefile.inc	cpu/Makefile.inc: Clean up non-existing directory inclusion	2020-08-17 06:24:23 +00:00